The present invention relates generally to the field of integrated circuit manufacturing, and more specifically, to forming hard mask layers over air gaps or porous interlayer dielectric materials on a semiconductor substrate.
Low dielectric constant (low-k) materials are increasingly needed for use as interlayer dielectrics (ILDs) in semiconductor devices, to reduce RC delay and improve device performance. As devices sizes continue to shrink, the dielectric constant of the material between metal lines must decrease to maintain the improvement. For example, some integrated circuit devices are expected to require dielectric materials with k<2 in the near future. To produce dielectric materials having such low dielectric constants, greater porosity is required, or air gaps may be created between the metal lines. However, unlanded via formation is difficult to integrate with air gaps or on top of porous dielectric layers because the etch process cannot be controlled sufficiently to prevent unwanted metal deposition in various areas of the device.
In semiconductor devices, vias connect different layers of metal lines or electrically conductive materials. An insulator or dielectric material may be formed between separate planes of conductive material around the vias and also within the trenches in the circuit pattern of a layer of conductive material.
In the past, vias usually have been formed as landed vias (i.e., the via rests entirely on a conductive layer) rather than unlanded vias (i.e., the via rests partially on a conductive layer and partially on an insulator). For example, unlanded vias may result from some misalignment of masks that are used to form the openings in dielectric layers. As packing density of integrated circuits increase, and device geometries decrease, very slight misalignment, lithography, or etch registration errors may result in unlanded vias. To avoid the risk of poor electrical connections or device failure, efforts have been made to exclude unlanded vias from design rules, or to specify increasingly restrictive alignment tolerances to prevent unlanded vias. However, unlanded vias cannot be eliminated completely if higher packing densities are to be achieved.
Thus, unlanded vias may be necessarily encountered in semiconductor processing as devices shrink and packing densities increase. One such process is a dual damascene process that involves forming both a via and a trench in a dielectric layer or interlayer dielectric. After the via and trench are etched, they may be filled with a conductive material such as copper to form a complete conductive layer of interconnects.
In some processes, such as dual damascene processes, hard mask layers have been added, at least in part to handle unlanded vias. For example, a hard mask layer may provide an etch stop, i.e., to block or prevent conductive material in an unlanded via, or dry or wet etch chemicals used to form an unlanded via, from breaking through and/or spilling into one or more underlying layers and cause irretrievable damage to those layers. The lower layers that may be adversely affected include air gap layers or low-k dielectric materials that may have significant porosity. If the air gaps or porous dielectric layers are not isolated from etching steps, subsequent processing may provide the unwanted result of filling that gap or layer with metal.
Materials that have been used to form such protective hard mask layers include silicon oxide, silicon nitride or silicon carbide. Not only are the hard masks intended to prevent the etching steps from damaging dielectric or air gap layers below unlanded vias, but they also should provide mechanical support to build layers over the Lard mask layer. However, the materials that have been used for hard mask layers generally have a dielectric constant (k) of at least 5.0. As a result, hard mask layers tend to increase the overall effective dielectric constant of the dielectric stack. Additionally, the etch selectivity of a silicon nitride or silicon carbide hard mask layer to a dielectric material such as carbon doped oxide (CDO) is only in the range of approximately 2:1 or 3:1 for manufacturable etch processes, so there is a risk that the etching steps could penetrate hard mask that is thin.
What is needed is a thin hard mask layer over an air gap or dielectric material, in which the thin hard mask has an etch selectivity to the dielectric material substantially greater than 2:1 or 3:1. A hard mask layer also is needed for use in dual damascene and other multilayer semiconductor processes, that will contribute to a lower keff value, thereby reducing RC delay. A hard mask layer is needed that will allow diffusion of sacrificial material or pore-forming material therethrough to form air gaps or pores. A hard mask layer and method are needed that will allow use of unlanded vias and decrease the risk that etching steps could penetrate through to underlying layers. A hard mask layer is needed for semiconductor manufacturing process that will contribute to less restrictive, and therefore less costly, tolerances.